{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544471453219 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544471453234 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 14:50:52 2018 " "Processing started: Mon Dec 10 14:50:52 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544471453234 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544471453234 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off hexkeypad -c hexkeypad " "Command: quartus_map --read_settings_files=on --write_settings_files=off hexkeypad -c hexkeypad" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544471453234 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544471454855 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544471454855 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "hexkeypad.v(125) " "Verilog HDL warning at hexkeypad.v(125): extended using \"x\" or \"z\"" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 125 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1544471464152 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hexkeypad.v 1 1 " "Found 1 design units, including 1 entities, in source file hexkeypad.v" { { "Info" "ISGN_ENTITY_NAME" "1 hexkeypad " "Found entity 1: hexkeypad" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544471464184 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544471464184 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "hexkeypad " "Elaborating entity \"hexkeypad\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544471464293 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 hexkeypad.v(114) " "Verilog HDL assignment warning at hexkeypad.v(114): truncated value with size 32 to match size of target (28)" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 114 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544471464309 "|hexkeypad"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "led\[9\] hexkeypad.v(24) " "Output port \"led\[9\]\" at hexkeypad.v(24) has no driver" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1544471464309 "|hexkeypad"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio\[14..13\] hexkeypad.v(23) " "Output port \"gpio\[14..13\]\" at hexkeypad.v(23) has no driver" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1544471464309 "|hexkeypad"}
{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidirectional pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "row\[0\] " "bidirectional pin \"row\[0\]\" has no driver" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1544471465980 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "row\[1\] " "bidirectional pin \"row\[1\]\" has no driver" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1544471465980 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "row\[2\] " "bidirectional pin \"row\[2\]\" has no driver" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1544471465980 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "row\[3\] " "bidirectional pin \"row\[3\]\" has no driver" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1544471465980 ""}  } {  } 0 13039 "The following bidirectional pins have no drivers" 0 0 "Analysis & Synthesis" 0 -1 1544471465980 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[9\] GND " "Pin \"led\[9\]\" is stuck at GND" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1544471466121 "|hexkeypad|led[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "gpio\[13\] GND " "Pin \"gpio\[13\]\" is stuck at GND" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1544471466121 "|hexkeypad|gpio[13]"} { "Warning" "WMLS_MLS_STUCK_PIN" "gpio\[14\] GND " "Pin \"gpio\[14\]\" is stuck at GND" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1544471466121 "|hexkeypad|gpio[14]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1544471466121 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544471466215 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[0\] row\[0\] " "Output pin \"led\[0\]\" driven by bidirectional pin \"row\[0\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466387 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[0\] row\[0\] " "Output pin \"gpio\[0\]\" driven by bidirectional pin \"row\[0\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466387 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[1\] row\[1\] " "Output pin \"led\[1\]\" driven by bidirectional pin \"row\[1\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466387 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[1\] row\[1\] " "Output pin \"gpio\[1\]\" driven by bidirectional pin \"row\[1\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[2\] row\[2\] " "Output pin \"led\[2\]\" driven by bidirectional pin \"row\[2\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[2\] row\[2\] " "Output pin \"gpio\[2\]\" driven by bidirectional pin \"row\[2\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[3\] row\[3\] " "Output pin \"led\[3\]\" driven by bidirectional pin \"row\[3\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[3\] row\[3\] " "Output pin \"gpio\[3\]\" driven by bidirectional pin \"row\[3\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[4\] col\[0\] " "Output pin \"led\[4\]\" driven by bidirectional pin \"col\[0\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[4\] col\[0\] " "Output pin \"gpio\[4\]\" driven by bidirectional pin \"col\[0\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[5\] col\[1\] " "Output pin \"led\[5\]\" driven by bidirectional pin \"col\[1\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[5\] col\[1\] " "Output pin \"gpio\[5\]\" driven by bidirectional pin \"col\[1\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[6\] col\[2\] " "Output pin \"led\[6\]\" driven by bidirectional pin \"col\[2\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[6\] col\[2\] " "Output pin \"gpio\[6\]\" driven by bidirectional pin \"col\[2\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "led\[7\] col\[3\] " "Output pin \"led\[7\]\" driven by bidirectional pin \"col\[3\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 24 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "gpio\[7\] col\[3\] " "Output pin \"gpio\[7\]\" driven by bidirectional pin \"col\[3\]\" cannot be tri-stated" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 23 -1 0 } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 21 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1544471466402 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "22 " "22 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1544471466980 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "W:/verilog DE1-SoC/hex_keypad _PMOD/output_files/hexkeypad.map.smsg " "Generated suppressed messages file W:/verilog DE1-SoC/hex_keypad _PMOD/output_files/hexkeypad.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544471467152 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544471468027 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544471468027 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "swt\[1\] " "No output dependent on input pin \"swt\[1\]\"" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 17 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1544471468621 "|hexkeypad|swt[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "swt\[2\] " "No output dependent on input pin \"swt\[2\]\"" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 17 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1544471468621 "|hexkeypad|swt[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "swt\[3\] " "No output dependent on input pin \"swt\[3\]\"" {  } { { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 17 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1544471468621 "|hexkeypad|swt[3]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1544471468621 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "175 " "Implemented 175 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544471468621 ""} { "Info" "ICUT_CUT_TM_OPINS" "33 " "Implemented 33 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544471468621 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1544471468621 ""} { "Info" "ICUT_CUT_TM_LCELLS" "129 " "Implemented 129 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544471468621 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544471468621 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "722 " "Peak virtual memory: 722 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544471468840 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 14:51:08 2018 " "Processing ended: Mon Dec 10 14:51:08 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544471468840 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544471468840 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544471468840 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544471468840 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1544471471727 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544471471727 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 14:51:10 2018 " "Processing started: Mon Dec 10 14:51:10 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544471471727 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1544471471727 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off hexkeypad -c hexkeypad " "Command: quartus_fit --read_settings_files=off --write_settings_files=off hexkeypad -c hexkeypad" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1544471471727 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1544471471930 ""}
{ "Info" "0" "" "Project  = hexkeypad" {  } {  } 0 0 "Project  = hexkeypad" 0 0 "Fitter" 0 0 1544471471930 ""}
{ "Info" "0" "" "Revision = hexkeypad" {  } {  } 0 0 "Revision = hexkeypad" 0 0 "Fitter" 0 0 1544471471930 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1544471472539 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1544471472539 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "hexkeypad 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"hexkeypad\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1544471472758 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544471472820 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544471472820 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1544471473258 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1544471473722 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1544471483644 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk~inputCLKENA0 10 global CLKCTRL_G6 " "clk~inputCLKENA0 with 10 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1544471483738 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1544471483738 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544471483738 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1544471483753 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544471483753 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544471483753 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1544471483753 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1544471483753 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1544471483753 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "hexkeypad.sdc " "Synopsys Design Constraints File file not found: 'hexkeypad.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1544471484566 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1544471484566 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1544471484566 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1544471484566 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1544471484566 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1544471484582 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1544471484582 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1544471484582 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544471484628 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1544471489722 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1544471489957 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544471490988 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1544471491769 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1544471493035 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544471493035 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1544471494504 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "W:/verilog DE1-SoC/hex_keypad _PMOD/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1544471498785 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1544471498785 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1544471501254 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1544471501254 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544471501254 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.47 " "Total time spent on timing analysis during the Fitter is 0.47 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1544471503395 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544471503457 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544471504160 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544471504160 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544471504942 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544471507832 ""}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "4 " "Following 4 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "row\[0\] a permanently disabled " "Pin row\[0\] has a permanently disabled output enable" {  } { { "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" { row[0] } } } { "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row\[0\]" } } } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 0 0 } } { "temporary_test_loc" "" { Generic "W:/verilog DE1-SoC/hex_keypad _PMOD/" { { 0 { 0 ""} 0 20 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1544471508176 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "row\[1\] a permanently disabled " "Pin row\[1\] has a permanently disabled output enable" {  } { { "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" { row[1] } } } { "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row\[1\]" } } } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 0 0 } } { "temporary_test_loc" "" { Generic "W:/verilog DE1-SoC/hex_keypad _PMOD/" { { 0 { 0 ""} 0 21 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1544471508176 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "row\[2\] a permanently disabled " "Pin row\[2\] has a permanently disabled output enable" {  } { { "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" { row[2] } } } { "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row\[2\]" } } } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 0 0 } } { "temporary_test_loc" "" { Generic "W:/verilog DE1-SoC/hex_keypad _PMOD/" { { 0 { 0 ""} 0 30 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1544471508176 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "row\[3\] a permanently disabled " "Pin row\[3\] has a permanently disabled output enable" {  } { { "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/desl/quartus18/quartus/bin64/pin_planner.ppl" { row[3] } } } { "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/desl/quartus18/quartus/bin64/Assignment Editor.qase" 1 { { 0 "row\[3\]" } } } } { "hexkeypad.v" "" { Text "W:/verilog DE1-SoC/hex_keypad _PMOD/hexkeypad.v" 20 0 0 } } { "temporary_test_loc" "" { Generic "W:/verilog DE1-SoC/hex_keypad _PMOD/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1544471508176 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1544471508176 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "W:/verilog DE1-SoC/hex_keypad _PMOD/output_files/hexkeypad.fit.smsg " "Generated suppressed messages file W:/verilog DE1-SoC/hex_keypad _PMOD/output_files/hexkeypad.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1544471508426 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2570 " "Peak virtual memory: 2570 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544471511645 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 14:51:51 2018 " "Processing ended: Mon Dec 10 14:51:51 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544471511645 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Elapsed time: 00:00:41" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544471511645 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:05 " "Total CPU time (on all processors): 00:01:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544471511645 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1544471511645 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1544471515504 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544471515520 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 14:51:55 2018 " "Processing started: Mon Dec 10 14:51:55 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544471515520 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1544471515520 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off hexkeypad -c hexkeypad " "Command: quartus_asm --read_settings_files=off --write_settings_files=off hexkeypad -c hexkeypad" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1544471515520 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1544471516923 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1544471522215 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "718 " "Peak virtual memory: 718 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544471524371 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 14:52:04 2018 " "Processing ended: Mon Dec 10 14:52:04 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544471524371 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544471524371 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544471524371 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1544471524371 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1544471525450 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1544471526694 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544471526710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 14:52:05 2018 " "Processing started: Mon Dec 10 14:52:05 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544471526710 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1544471526710 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta hexkeypad -c hexkeypad " "Command: quartus_sta hexkeypad -c hexkeypad" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1544471526710 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #2" {  } {  } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1544471526898 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1544471528101 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1544471528101 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471528148 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471528148 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "hexkeypad.sdc " "Synopsys Design Constraints File file not found: 'hexkeypad.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1544471529085 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471529085 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1544471529085 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name counter\[10\] counter\[10\] " "create_clock -period 1.000 -name counter\[10\] counter\[10\]" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1544471529085 ""}  } {  } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544471529085 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1544471529085 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544471529085 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1544471529085 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1544471529257 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1544471529366 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1544471529366 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.556 " "Worst-case setup slack is -4.556" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.556             -13.738 clk  " "   -4.556             -13.738 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.789             -78.683 counter\[10\]  " "   -2.789             -78.683 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529413 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471529413 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.470 " "Worst-case hold slack is 0.470" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529491 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529491 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.470               0.000 clk  " "    0.470               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529491 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.566               0.000 counter\[10\]  " "    0.566               0.000 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529491 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471529491 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471529538 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471529585 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.465 " "Worst-case minimum pulse width slack is -0.465" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529663 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529663 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.465              -6.038 clk  " "   -0.465              -6.038 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529663 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -17.899 counter\[10\]  " "   -0.394             -17.899 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471529663 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471529663 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544471529741 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1544471529773 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1544471530820 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544471531085 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1544471531132 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1544471531132 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.460 " "Worst-case setup slack is -4.460" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531179 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531179 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.460             -14.501 clk  " "   -4.460             -14.501 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531179 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.768             -77.778 counter\[10\]  " "   -2.768             -77.778 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531179 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471531179 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.461 " "Worst-case hold slack is 0.461" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.461               0.000 clk  " "    0.461               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.545               0.000 counter\[10\]  " "    0.545               0.000 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531226 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471531226 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471531273 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471531320 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.492 " "Worst-case minimum pulse width slack is -0.492" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.492              -6.405 clk  " "   -0.492              -6.405 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -17.665 counter\[10\]  " "   -0.394             -17.665 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471531382 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471531382 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1544471531445 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1544471531820 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1544471532757 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544471533007 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1544471533007 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1544471533007 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.411 " "Worst-case setup slack is -3.411" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.411              -4.820 clk  " "   -3.411              -4.820 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.348             -36.598 counter\[10\]  " "   -1.348             -36.598 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533054 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471533054 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.231 " "Worst-case hold slack is 0.231" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533101 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533101 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.231               0.000 clk  " "    0.231               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533101 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.294               0.000 counter\[10\]  " "    0.294               0.000 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533101 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471533101 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471533163 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471533210 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.499 " "Worst-case minimum pulse width slack is -0.499" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.499              -1.559 clk  " "   -0.499              -1.559 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.055               0.000 counter\[10\]  " "    0.055               0.000 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533273 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471533273 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544471533320 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544471533867 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1544471533867 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1544471533867 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.881 " "Worst-case setup slack is -2.881" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.881              -4.019 clk  " "   -2.881              -4.019 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.188             -31.962 counter\[10\]  " "   -1.188             -31.962 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533929 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471533929 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.223 " "Worst-case hold slack is 0.223" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.223               0.000 clk  " "    0.223               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.264               0.000 counter\[10\]  " "    0.264               0.000 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471533976 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471533976 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471534023 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544471534085 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.497 " "Worst-case minimum pulse width slack is -0.497" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471534132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471534132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.497              -1.518 clk  " "   -0.497              -1.518 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471534132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.082               0.000 counter\[10\]  " "    0.082               0.000 counter\[10\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544471534132 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544471534132 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544471537773 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544471537773 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1032 " "Peak virtual memory: 1032 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544471538304 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 14:52:18 2018 " "Processing ended: Mon Dec 10 14:52:18 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544471538304 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544471538304 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544471538304 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1544471538304 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1544471540679 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544471540726 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 14:52:20 2018 " "Processing started: Mon Dec 10 14:52:20 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544471540726 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1544471540726 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off hexkeypad -c hexkeypad " "Command: quartus_eda --read_settings_files=off --write_settings_files=off hexkeypad -c hexkeypad" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1544471540726 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1544471542768 ""}
{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1544471542909 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "hexkeypad.vo W:/verilog DE1-SoC/hex_keypad _PMOD/simulation/modelsim/ simulation " "Generated file hexkeypad.vo in folder \"W:/verilog DE1-SoC/hex_keypad _PMOD/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544471543591 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "632 " "Peak virtual memory: 632 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544471544044 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 14:52:24 2018 " "Processing ended: Mon Dec 10 14:52:24 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544471544044 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544471544044 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544471544044 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1544471544044 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 46 s " "Quartus Prime Full Compilation was successful. 0 errors, 46 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1544471545154 ""}
